Spin-torque transfer random access memory (STT-RAM) is a promising emerging non-volatile memory (NVM) technology because of its fast read & write times (<10 ns) as well as its potential to have infinite cycling endurance (>1015), thus making it a viable candidate to replace not only NVM such as Flash Memory but also dynamic random access memory (DRAM) and static random access memory (SRAM). The key element of this memory is a magnetic tunnel junction (MTJ) which consists of two ferromagnetic (FM) layers (e.g., CoFe, CoFeB, NiFe, and the like) separated by a tunnel barrier layer (e.g., Al2O3, MgO, and the like). If the tunneling current in this MTJ is spin-polarized current (i.e., with all the injected electrons possessing only one of the two spin states), the resistance of the stack during a short duration or read operation, depends upon whether the magnetization of the two FM layers are parallel or anti-parallel to each other. Typically, the magnetization of one of the FM layers is fixed or “pinned” by antiferromagnetic coupling to a stack (e.g. Ru/IrMn, and the like) whereas the other FM layer is allowed to be “free” (i.e., have either parallel or anti-parallel magnetization). Furthermore, a magnetic field may be required during deposition of the FM layers or post-deposition annealing to align the magnetization orientation in the thin films. The “write” operation can be achieved by passing a pulsed current with spin-polarized electrons through the MTJ, which switches the magnetic orientation of the free FM layer due to a combination of spin-torque transfer and thermal heating at sufficiently high current density (Jc). In addition, the stack may have additional layers such as Ta as a capping layer and also as a seed layer for orienting the texture or grain structure of the subsequent films to enhance the magnetic and electrical properties. Furthermore, additional ferromagnetic layers (e.g. CoPd and NiFe, and the like) may be used to enhance the electron spin-polarization and minimize stray magnetic fields. To form a large memory array consisting of multiple memory cells, the STT-RAM stack needs to be integrated with a current steering element such as a transistor or a diode which allows the bit to pass current through it for read or write operations only when it is “selected”, thus minimizing the leakage paths in the memory array.
One of the challenges for STT-RAM is the high current density (Jc) required for “write” operation (i.e., to change the orientation of the “free” FM layer, typically ˜100 uA for ˜54 nm minimum feature size), which is significantly higher than the write currents for Flash memory. While this current scales with area proportionally, lower currents are required for this technology to be cost competitive. Some of the approaches for this write current reduction include orienting the magnetization of the FM layers perpendicular instead of in the plane of the film. Another challenge for STT-RAM is to have sufficient signal-to-noise for the read operation (i.e., >100 mV sense voltage signal) due to different resistances of the MTJ with parallel or anti-parallel magnetizations or having a high tunnel magnetoresistance (TMR) ratio. Approaches to increase TMR include optimization of the FM layers (e.g., CoFeB), and/or the tunnel barrier layer (e.g., MgO), or having a dual MTJ stack. Thus, there is need for optimization or improvement of the materials and stacks used for STT-RAM.